A data buffer, such as a FIFO memory buffer, is typically used to interface a source of data with a port circuit of a packet switch. In certain instances, a port circuit may serve a plurality of sources of data associated with different grades of service, including, for example, latency, reliability, bandwidth, etc. In such a situation, a data buffer is provided for each data source, with the data buffer sized to handle the transfer of a large file, taking into account the throughput of the associated packet switch. It can be appreciated, therefore, that if a port circuit is serving a large number of data sources, e.g., 512, then the port would have to be equipped with an equal number of data buffers. It can also be appreciated that the administration of a large number of data buffers would indeed be a complex task, thereby making the associated port circuit complex. Moreover, if each buffer is formed from a large number of memory locations, then the cost of equipping a port circuit with a large number of buffers would indeed be expensive.